library IEEE;
use ieee.std_logic_1164.all;


	


package package_red is

	type arreglo is array(0 to (15)) of STD_LOGIC_VECTOR(7 downto 0);	
	
	component mux IS
	PORT
	(
		a		: IN	STD_LOGIC_VECTOR(7 downto 0);
		sel		: IN 	STD_LOGIC_VECTOR(1 downto 0);
		b,c,d,e	: OUT	STD_LOGIC_VECTOR(7 downto 0)
	);
	end component;
	
	component demux IS
	PORT
	(
		sel		: IN 	STD_LOGIC_VECTOR(1 downto 0);
		b,c,d,e	: IN	STD_LOGIC_VECTOR(7 downto 0);
		a		: OUT	STD_LOGIC_VECTOR(7 downto 0)
	);
	end component;
	
end package_red;
